ELE5758
Practical Exercise
Tasks: Use Vivado, Zedboard, and the provided data to perform. and report the following exercises
Q1. Implement (by writing the RTL code) and simulate a 16-point 8-bit FFT FPGA module.
Q2. Convert the simulated FFT module to an IP and name it according to your group.
Q3. Use the IP to implement and evaluate a circular convolution module. Validate the result and determine the resource utilization, timing report, and latency of the convolution module (Hint: Use no. of clock cycles).
Note: Use the following as the input and weight values
input = [ -8 10 - 10 6 7 8 -9 -2 -5 6 - 1 9 -7 -5 -7 -8 ]
weights = [ 5 3 3 0 5 3 2 3 2 0 1 0 1 1 2 0]
THE CONVOLUTION ILLUSTRATION USING MATLAB
in = [ -8 10 - 10 6 7 8 -9 -2 -5 6 - 1 9 -7 -5 -7 -8 ];
weights = [5 3 3 0 5 3 2 3 2 0 1 0 1 1 2 0];
in_FFT = fft(in);
weights_FFT = fft(weights);
pt_wise_mul = in_FFT.*weights_FFT;
convolution = ifft(pt_wise_mul);
%%%%-- verify -----
convolution_base = cconv(in, weights, 16);
isequal(convolution, convolution_base)
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