代做RV32I、Python/c++程序语言代写

日期：2024-05-01 11:15

Tasks

Implement datapath components in RV32I single-cycle processor

2

Control Logic (Decoder)

Tasks

n Implement the Controller

n Impelment the Single-cycle Processor using

p Datapath components implemented in Lab4

– You need to load your Lab4 circ file as a library for using them

p Controller implemented in this Lab

n Test your implementations using

p TestController

p TestRV32I

3

Implement the Controller

n Instructions to support

p Instructions covered in class,

p ECALL instruction

– We use it in a simple way: once the processor encounters an

ECALL instruction, it sets the Halt signal to 1, and the processor

should stop execution (i.e., PC should not be updated any more,

making the processor halts at the ECALL instruction forever)

n You need to implement totally xxx instructions

p See the next slide for more details...

Test Your Controller

n A tester named TestController has been provided to

faciliate your testing of your controller locally

p You can upload and test your implementation on EduCoder

after passing the local test, this will reduce your effort

n The tester is almost done

p Test vectors for the 30 instructions, as well as their

combinations with BrEq/BrLT input signals have been

provided in the corresponding ROMs, and there are 48

elements in each ROM for testing

p But the Result ROM is empty, and you need to fill it with

correct results (each result corresponds to the set of control

signals that should be produced by the controller)

p See the EXCEL file ctr-result.xlsx for more details...

6

Implement the Single-Cycle Processor

n The fetch stage has been given in addition to the input/output pins,

and the IMEM has already been filled with the Fib(6) program (our

processor lacks support for reading a parameter from keyboard)

n You need to implement the rest parts, some important issues include

p How to Halt the processor when encoutering the ECALL instruction?

– Hint: You can use the Halt control signal to disable clock input to PC,

therefore it will not be updated anymore

p The processor should support reading data from an address given by

the input pin Addr, and the data should be passed to the output pin

MData. This will enable us to test that your processor has correctly

executed the program, and the correct result has been writen to the

correct memory location

– Hint: The address input of the DMEM should be able to select from two input

addresses, one from ALU output, and another from the Addr input pin. The

Halt signal can be used to control which path to select

7

Test Your Processor

n The tester (TestRV32I) for your RV32I processor is

simple, but a couple of things to be reminded

p Before testing, you need to set the input pin Addr=0x2000,

because the final result of Fib(6) will be written to this

memory location, and the tester need to read this result from

0x2000

p When the program finished execution (by encountering the

ECALL instruction), the Halt signal becomes 1. Pay attention

to that, and you can check the result of MData to see

whether the it is 0xd (13 in decimal). If yes, your processor

works correctly, and you can upload it to EduCoder for pass

testing.

p The ICount output pin gives the number of instructions that

have been executed, and the PCOut pin gives the address of

currrent instruction

8

List of Files

n RV32I.circ

p The framework of the circuits that you need to implement

n ctr-inst.asm

p The source file containing all instructions and BrEq/BrLT combinations for testing your

controller

n ctr-inst.hex

p The binary of ctr-inst.asm (in textual hex) that has been loaded into the Inst ROM in

TestController

n ctr-breq.hex, ctr-brlt.hex

p The combinations of BrEq/BrLT that are used as input for testing your Controller, which have

been loaded into the BrEq and BrLT ROMs

n ctr-result.xlsx

p The Truth Table for testing your controller. You need to fill it by yourself, and use it to

generate te ctr-result.hex file.

n ctr-result.hex

p The correct result of the generated control signals to compare with the control signals

generated by your controller. You need to load it into the Result_S ROM.

n fib.asm

p The source file of the Fib(6) used for testing your RV32I processor

n fib.hex

p The executable (in textual hex) of Fib(6) that has been loaded into the IMEM

9

The End

10