Course Name and Code: ELEC0004 Digital Electronics
Coursework description: Assignment 2
ANSWER BOTH QUESTIONS
1. A JK flip-flop receives a clock and two inputs, J and K. On the rising edge of the clock, it updates the output, Q. If J and K are both 0, Q retains its current value. If only J is 1, Q becomes 1. If only K is 1, Q becomes 0. If both J and K are 1, Q becomes the opposite of its current value.
(i) Sketch the state transition diagram for the JK flip-flop. [10 marks]
(ii) Write out the state transition table for the JK flip flop. [10 marks]
(iii) Construct a JK flip-flop based on a D flip-flop and next-state combinational
logic. Your design should be in the form of a Moore-type finite state machine. [30 marks]
2. A toggle (T) flip-flop receives a clock and one input, T. On the rising edge of the
clock, it updates the output, Q. If T is 0, Q retains its current value. If T is 1, Q toggles to the complement of its current value (i.e., Q becomes the opposite of its current value).
(i) Sketch the state transition diagram for the T flip-flop. [10 marks]
(ii) Write out the state transition table for the T flip flop. [10 marks]
(iii) Construct a T flip-flop based on a D flip-flop and next-state combinational
logic. Your design should be in the form of a Moore-type finite state machine. [30 marks]
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