Department of Electrical and Electronic Engineering
EIE2105 Digital and Computer Systems
Tutorial 3: Combinational Logic II
Q1. The truth table of a logic circuit is given as follows.
|
input |
output |
||||
|
A |
B |
C |
X |
Y |
Z |
|
0 |
0 |
0 |
0 |
0 |
0 |
|
0 |
1 |
0 |
1 |
1 |
1 |
|
0 |
0 |
1 |
0 |
0 |
1 |
|
0 |
1 |
1 |
0 |
1 |
0 |
|
1 |
0 |
0 |
1 |
1 |
1 |
|
1 |
1 |
0 |
0 |
1 |
0 |
|
1 |
0 |
1 |
1 |
0 |
1 |
|
1 |
1 |
1 |
1 |
0 |
0 |
a. Implement the circuit with 8-to-1 multiplexers.
b. Implement the circuit with a 3-to-8 decoder and, if necessary, some additional OR gates.
Q2. The truth table of a priority encoder has been given as follows.
|
Inputs |
Outputs |
|||||
|
D3 |
D2 |
D1 |
D0 |
A1 |
A0 |
V |
|
0 |
0 |
0 |
0 |
X |
X |
0 |
|
0 |
0 |
0 |
1 |
0 |
0 |
1 |
|
0 |
0 |
1 |
X |
0 |
1 |
1 |
|
0 |
1 |
X |
X |
1 |
0 |
1 |
|
1 |
X |
X |
X |
1 |
1 |
1 |
a. What is the implied priority order of inputs D0, D1, D2 and D3 in this encoder?
b. Modify the truth table such that the priority order becomes D2 > D3 > D1 > D0.
c. Based on the modification result obtained in (b), write down the Boolean functions for outputs A1, A0 and V. You should simplify the functions with K-map in your answer (show the steps in details).
d. Draw the circuit diagram of the modified encoder by using simple logic gates (i.e., 2-input AND, 2-input OR, and NOT gates).
e. Can you reduce the number of logic gates by gate sharing? Give the number of used logic gates and draw the corresponding circuit.
f. What is the literal cost and the gate input cost of your circuit at the end?
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