代写ENGD3001 Advanced Digital Design Assignment 1帮做R编程

日期：2025-01-24 06:34

Module name:		Advanced Digital Design
Module code:		ENGD3001
Title of the Assignment:		Assignment 1
This coursework item is:			Formative
This coursework will be marked anonymously:			Yes
The module learning outcomes that are assessed by this coursework are: 1.   “Knowledge and specialist analytic development techniques in the areas of VLSI design, ASM design and implementation, and VHDL design.” 2.   “Development of generic and transferable skills in advanced digital system design methodologies using industry standard design tools.”
This coursework is:			Individual
This coursework constitutes 40% to the overall module mark.
Date Set:		18 Nov 2024 (Week 8)
Date & Time Due:		by 12:00 noon on Monday, 17 Feb 2025 (Week 21)
When completed you are required to submit the following: Submit an electronic copy of your assignment via Learning Zone by the advertised deadline. Please note that you can only make one submission and once a submission is made it is final. No resubmissions or later additions are allowed under any circumstances, and by any means, so please double check that your report is correct and complete before submitting it.

Assignment 1

Design a 4-bit universal decimal counter in VHDL using behavioural modelling, as presented below:

LD     – Synchronous Parallel Load

D3,…,D0 – Parallel Data Inputs

Q3,…,Q0 – Data Outputs

RST   – Asynchronous Reset Input

UD    – Count direction (up/down)

The operation of the universal counter is described by the following function table:

RST  LD		UD	Action
0       x		x	Asynchronous Reset
1	0	0	Count Down
1	0	1	Count Up
1	1	x	Synchronous Parallel Load

Simulate this design with the aid of a ‘graphical testbench’ (also known as a “University Program VWF” file), using the Intel Quartus Prime Lite v23.1 software.

It is a mandatory requirement of this assignment to use the correct software and the correct type of testbench. Failure to adhere to any of the mandatory assignment requirements will result in a mark of zero.

What you should submit

You should submit a formal report explaining your design and your results.

Specifically, your report should contain at least the following information:

a)  An introduction including the design brief,

b)  A background section on counters, their types and their operation,

c)  A section explaining how you’ve solved the design task given to you and if applicable why you’ve selected a particular solution out of several possible,

d)  The complete listing of the code you’ve written, bearing in mind good programming and design practice,

e)  A legible screenshot of your graphical testbench (or testbenches if using more than one),

f)  The results of the simulations carried out (i.e. suitable, legible and detailed simulation waveforms) accompanied by detailed comments and explanations, and

g)  Conclusions (and possible further improvements if applicable).