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日期：2024-02-06 09:13

Exercises Set#1: VHDL

Create a new Copy of the Tutorial ISE project

1. Copy the project folder of the previous Tutorial and rename the copy as

exercises_1

2. Go to the new created folder, and open the ISE project file. It should show

you the same files and design hierarchy that you have created during the

Tutorial

Exercise 1

1. Edit the top2.vhd file, copying the architecture arch or top2 and paste it

bellow

2. Change the name of the copied architecture to arch2

3. Comment all the code of the architecture arch1 (select the lines of the code

you want to comment, press right button of the mouse in order to present a

contextual menu, and click on Comment>Line(s) )

4. On the architecture arch2, change the description of the registers (which is

in the ledcontrol process) as:

ledcontrol: process(rst,clk) begin

if rst='1' then

led_i<="0001";

elsif rising_edge(clk) and ps0_o='1' then

led_i<=led_i(1 to 3)&led_i(0);

end if;

end process;

5. Synthetize the circuit top2(arch2) and view the synthesized result on View

RTL Schematic

6. Implement the layout of the circuit and view it on View/Edit Routed Design.

7. Briefly comment the main difference of the arch2 when compared with arch,

in the synthesised circuit and in the layout due to the change done in the

process. Justify the results.

Exercise 2

1. Uncomment the architecture arch (select the lines of the code you want to

uncomment, press right button of the mouse in order to present a contextual

menu, and click on Uncomment>Line(s) )

2. Copy again arch and paste it bellow arch2 and comment the arch2 again.

Rename the new copy of arch to arch3, and modify it as:

architecture arch3 of top2 is

signal ps0_o: std_logic;

signal cnt: unsigned(0 to 1);

begin

ps0: entity work.prescaler(a1d) generic map(10e+6)

port map(clk,rst,ps0_o);

cnt0: process begin

wait until rising_edge(clk);

if rst='1' then

cnt<=(others=>'1');

elsif ps0_o='1' then

cnt<=cnt-1;

end if;

end process;

led(0)<='1' when cnt=0 else '0';

led(1)<='1' when cnt=1 else '0';

led(2)<='1' when cnt=2 else '0';

led(3)<='1' when cnt=3 else '0';

end architecture;

3. Since the new description uses the unsigned type to perform the subtraction

and comparators on the signal cnt, include the library ieee.std_logic_arith at

the top of the top2.vhdl file

library IEEE;

use IEEE.STD_LOGIC_1164.ALL;

use ieee.std_logic_arith.all;

4. Create a testbench to perform the functional simulation of the VHDL code for

arch and arch3. You can write it at the bottom of the top2.vhd file

--synthesis translate_off

library IEEE;

use IEEE.STD_LOGIC_1164.ALL;

entity tb_top2 is

end entity;

architecture tb1 of tb_top2 is

constant TCLK: time:=10 ns;

signal clk: std_logic:='0';

signal rst: std_logic;

signal led_0,led_1: std_logic_vector(0 to 3);

begin

dut0: entity work.top2(arch) port map(clk,rst,led_0);

dut1: entity work.top2(arch3) port map(clk,rst,led_1);

clk<=not clk after TCLK/2;

rst<='1','0' after 10*TCLK;

end architecture;

--synthesis translate_on

5. In order to get a faster simulation, change the ps0 generic value (from

10e+6) to a much lower value (for instance 5) in both architectures (arch and

arch3)

ps0: entity work.prescaler(a1d) generic map(5)

6. Simulate the testbench and compare the simulation differences between the

led_0 (output for arch) and led_1 (output for arch3). Justify the results

7. Comment the architecture arch, in order to have a unique architecture arch3

for the entity top2

8. Change the prescaler number of counts (as it was at the beginning) in arch

and arch3

ps0: entity work.prescaler(a1d) generic map(10e+6)

9. Synthetize the circuit top2(arch3) and view the synthesized result on View

RTL Schematic

10. Implement the layout of the circuit and view it on View/Edit Routed Design.

11. Briefly comment the main difference of the arch3 when compared with arch,

in the synthesised circuit and in the layout due to the change done in the

process. Justify the results.

Exercise 3

1. Comment all the architectures of top2

2. Modify the entity top2, in order to parametrize the number of leds to control

(with the generic NLED) among with the number of counts of the prescaler

(PSCOUNTS) as:

entity top2 is

generic(

PSCOUNTS: integer:=10e+6;

NLED: integer:=4 );

port(

clk,rst: in std_logic;

led: out std_logic_vector(0 to NLED-1) );

end entity;

3. Uncomment arch, and modify it in order it will work with an arbitrary number

for NLED (complete the following code and report it)

architecture arch of top2 is

signal led_i: std_logic_vector(led'range);

signal ps0_o: std_logic;

begin

led<=led_i;

ps0: entity work.prescaler(a1d) generic map(PSCOUNTS)

port map(clk,rst,ps0_o);

ledcontrol: process begin

wait until rising_edge(clk);

if rst='1' then

led_i<=...

elsif ps0_o='1' then

led_i<=...

end if;

end process;

end architecture;

4. Uncomment arch3, and modify it in order it will work with an arbitrary

number for NLED (complete the following code and report it)

architecture arch3 of top2 is

signal ps0_o: std_logic;

constant NBIT: integer:=F_NBITS(NLED);

signal cnt: unsigned(NBIT-1 downto 0);

constant CNT_MAX: unsigned(cnt'range):=conv_unsigned(NLED-1,NBIT);

begin

ps0: entity work.prescaler(a1d) generic map(PSCOUNTS)

port map(clk,rst,ps0_o);

cnt0: process begin

wait until rising_edge(clk);

if rst='1' then

cnt<=CNT_MAX;

elsif ps0_o='1' then

...

cnt<=cnt-1;

...

end if;

end process;

gen0: for j in led'range generate

led(j)<=...;

end generate;

end architecture;

5. Since the arch3 uses the function F_NBITS defined in the package

pack_pract, include this package at the top of the top2.vhd file

library IEEE;

...

use work.pack_pract.all;

6. Modify the testhench tb_top2 (complete the following code and report it) in

order to perform simulation with an arbitrary number for the parameter NLED

and check that the new architectures arch and arch3 will work as expected.

for several values of NLED, such as 4, 8 and 10

architecture tb1 of tb_top2 is

constant PRESCALER_COUNTS: integer:=5;

constant NUM_LED: integer:=4;

...

signal led_0,led_1: std_logic_vector(...);

begin

dut0: entity work.top2(arch) generic map(...)

port map(clk,rst,led_0);

dut1: entity work.top2(arch3) generic map(...)

port map(clk,rst,led_1);

...

end architecture;

7. Change the default value for the generic NLED to 8 in the entity declaration

entity top2 is

generic(

...

NLED: integer:=8 );

port(

... );

end entity;

8. Synthetize and implement the new architecture arch (comment the arch3).

Briefly comment the results when compared with the solutions for the arch

obtained in the previous exercises. Justify the results

9. Synthesize and implement the new architecture arch3 (comment the arch),

Briefly comment the results when compared with the solutions for the arch3

obtained in the previous exercises. Justify the results

Exercise 4

1. Comment all the architectures, except the last architecture arch (which uses

the generic NLED)

2. Go to the synthesis options (Right click on Synthetize – XST, and click

Process Properties in the contextual menu). A new window appears where

the synthesizer options can be changed. Select Category ‘Xilinx Specific

Options’ and set ‘No’ to the ‘Pack I/O Registers into IOBs’.

3. Synthetize and implement the layout. View the synthetized result with ‘View

Technology Schematic’

4. Go to the synthesis options, but set ‘Yes’ to the ‘Pack I/O Registers into

IOBs’

5. Synthetize and implement the layout. View the synthetized result with ‘View

Technology Schematic’

6. Compare the synthesis result and layout in the both cases (Packing or not

I/O registers into IOBs). Briefly comment the differences in both cases.

Justify the results.