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日期:2020-10-15 11:42

CPSC 359 – Fall 2020

Assignment 2: A Joystick-Activated Digital Combination Lock

due: 0900h 19-Oct-2020

Background

In this assignment, you will program a sequential circuit to implement a digital combination lock. To open the lock,

the user will enter numbers using the coded joystick positions that you did for Assignment 1. While the circuit is very

specific to this task, it is a simplification of many of the elements of a CPU. Your program will be equivalent to the

microcode in a CPU that establishes the machine-code/assembly language for the device.

Objective

Design and implement a sequential logic circuit that opens a lock after a user has entered the correct 3-digit combination

with a joystick.

Details

Use the provided template as a starting point to implement the circuit (Figure 1). The full template contains a solution

to Assignment 1, so it will not be released until 48 hours after Assignment 1 is due. A template with the joystick

encoder removed will be available with the release of this assignment for those that want to start early.

On the middle-left portion of the template is where the user operates the lock. You will find a joystick and the

combinational logic from Assignment 1 to encode joystick positions as numbers to enter into the lock. There is also a

reset/lock button. The user will use this to to engage the lock, or restart after a combination has been partially entered.

In the lower-left of the template, there is a signal called open that is attached to an LED. Use this to indicate

whether the lock is open or closed.

The upper-middle portion of the template has the combinational logic to handle the lock combination. There are

three 4-bit constants at the top of the section – these determine the correct combination for the lock. The three 4-

bit registers at the bottom of that section will hold the numbers entered by the user trying to open the lock. Your

circuit must control the entry of numbers into those registers. There are three latch signals, one for each register, to

control when a number gets entered into the corresponding digit of the combination. A clear signal resets the entered

combination to 0-0-0 whenever the lock is reset or an entered combination fails. The three comparators and a 3-input

AND gate determine whether or not a correct combination has been entered – all three latched numbers must match

the corresponding constant for the output of the AND gate to go high.

There is a space in the lower-right portion of the template to place your sequenctial logic circuit.

Note the use of tunnels in the template. These are in the wiring menu of Logisim. You can think of them as a

named wire. Anywhere the name of the tunnels match, Logisim treats it as if you had connected a wire between the

two points. They are a nice way to keep your circuits organized (especially if you choose meaningful names) and

reduce the clutter in the rat’s nest of connections that you get without them.

The template circuit is sufficient to implement the combination lock by providing a sequential circuit to use/provide

the signals in the tunnels. Once you are comfortable that you understand the template, create a state diagram for the

lock.

Figure 1: Template circuit for the joystick-activated digital combination lock.

Finally, implement the your state diagram in a sequential circuit using a read-only memory (ROM), as discussed in

class. Your sequential controller will need a clock signal to drive it. If you then click Ticks Enabled under the Simulate

menu in Logisim, the lock should operate as specified.

What you need to do

To design the circuit and complete the assignment, you need to do the following.

1. Identify all the inputs and outputs for your sequential circuit.

2. Design a finite state machine that will produce the required signals to the circuit in the template.

3. Design the combinational logic (or ROM programming) to implement your finite state machine.

4. Implement your design in Logisim.

Deliverables

Turn in the following items for evaluation.

1. All written work to show the steps in your analysis and design for items 1 through 3 above.

2. All files for your Logisim implementation of your design.

Hints

1. Note, while you may use discrete logic gates to implement the combinational logic required for the state transitions,

you will find it easier and more practical to use a read-only memory (ROM) as described in class.

2. Drag and drop on the joystick can be difficult for this application. If you click then drag, the number you enter

will be for where the initial click occurred, not where you dragged to. I found it works better if you just do

single clicks in the regions for the numbers in the combination.

3. You can use the pointer tool to manually change the clock state and step through your state machine.

4. Probes on lines can help you to see what your circuit is doing while debugging.

5. I wrote a short Python program to help me with the ROM programming. It can save you a lot of time by allowing

you to specify your state machine operation in a table in python. There is an example with the course notes –

feel free to embellish.

Evaluation

1 Identification of input/output/state variables. 2pts

2 Finite state machine - does task correctly. 6pts

3 Design of combinational logic/ROM programming. 5pts

4 Logisim implementation - runs correctly. 5pts

5 Logisim implementation - inputs/outputs labelled. 2pts

Total 20pts

There is no team work. Each student should submit their own solution.

Late work

After the deadline and up to 24hrs late: -5pts. After 24hrs and up to 48hrs late: -10pts. Over 48hrs late: -20pts, i.e.,

no assignment will be accepted beyond 48hrs after the deadline.

Plagiarism

Submitted solutions must be your own work, and only your own work.

You may find that the design task for this assignment is similar to other well known circuits. Nevertheless, you

should go through the design process yourself, and submit your own work. If you do borrow from other sources, cite

the source and clearly indicate what you have borrowed, keeping in mind the design must be substantially your own.

If you cite your sources, worst case you may receive a reduced grade for borrowing too much. If you borrow, but do

not cite, that is plagiarism and academic misconduct. Plagiarism carries severe penalties as determined by the Faculty

of Science.

As a guideline, consider the 20-minute rule. Talk with your colleagues and consult other sources (cite them please).

Wait at least 20 minutes, then do your work to be sure that it is your own. Less then 20 minutes usually means that

you are merely copying work from the original source.


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